It is known that phase lock circuits or PLL (an acronym for Phase Lock Loop), are being increasingly used for the generation of high-frequency clock signals for electronic apparatuses, especially electronic processors and transmission systems, by means of comparison with a periodic reference signal which is generally of lower frequency. In the field of magnetic recording and of telecommunications, PLL circuits furthermore permit the recognition of the fundamental frequency of a signal which is modulated (in phase or frequency) and the generation of an unmodulated signal which has the same frequency and which serves as a basis for the discrimination and the recognition of the modulation impressed on the comparison signal.
In phase lock circuits, an element which is critical for the purposes of achieving the desired benefits of a very short lock time and of uniformity of the clock signal generated (i.e. of low jitter) is constituted by the voltage-controlled oscillator (which is known by the acronym VCO). In the embodiment which is most common, on account of the possibility of construction in integrated circuit form, a VCO consists of an odd number N of inversion logic elements, or delay cells, which elements are ring-connected in such a manner as to generate a square wave with a period equal to 29N.multidot..DELTA. where A is the propagation delay of each cell. The variable delay of each cell is controlled by the supply voltage of the cells, which is constituted by the difference between a constant supply voltage Vcc and a variable regulating voltage.
On account of its structure, this type of VCO is influenced by the variations of the supply voltage which, in the absence of appropriate measures, modify the operating frequency of the oscillator to the same extent as variations of the regulating voltage. If the variations of the supply voltage are very slow with a transient duration greater than the time constant of the phase lock circuit in which the oscillator is connected, the PLL is able to intervene, modifying the control voltage, in such a manner that the frequency of the oscillator does not vary. This can be done with the introduction of a temporary and negligible phase variation between the reference signal and the feedback signal generated by the oscillator (possibly frequency-divided). If, however, the voltage variation is very abrupt, the oscillator modifies the output frequency, which, in the course of a plurality of signal cycles, results in an unacceptable dephasing or skew between the reference signal on the input side at the PLL, and the output signal from the oscillator.
Normally, the skew is expressed as a time delay relative to the reference signal, that is to say with a time unit of measurement (for example nsec).
The skew may also be expressed as a phase delay relative to the reference signal, that is to say in radians or as a percentage of the period of the reference signal. As the voltage variations may have opposite signs and thus give rise to angular shifts in the sense of a lead or a delay, the maximum algebraic difference of the skews in the sense of a lead or a delay which are caused by the voltage variations is defined as jitter.
To limit this disadvantage (skew and jitter) it is typically necessary to introduce measures which permit the rejection of the noise from the supply voltage of the VCO. The noise rejection is conventionally expressed as the ratio between the skew caused by an unexpected variation of the supply voltage and the amplitude of the voltage variation. This is accordingly measured in sec/V or, if expressed as a phase delay in relation to the reference signal, in radians/V or the percentage of the period %/V. The rejection is therefore higher, the smaller the numerical value which expresses it.
The solutions proposed by the prior art for the purpose of achieving a noise rejection are essentially of three types:
A) A dedicated supply for the VCO, which supply is inherently free from noise. Unfortunately, this approach is costly and does not lend itself to the construction of PLLs which are integrated with other circuits in a single electronic component, such as, for example, a microprocessor. PA1 B) Construction of VCOs with delay stages having a differential structure. This approach permits the attainment of high noise rejection from the supply voltage, at the expense of a high degree of circuit complexity . PA1 C) Construction of VCOs with high-frequency negative feedback.
By way of example, in this last approach, a capacitive coupling between the terminal at voltage Vcc and the terminal at the regulating voltage VR permits the transfer to some extent of the noise of the voltage Vcc to the regulating terminal, and, thus, to the regulating voltage. However, the output impedance of this terminal, which is not negligible, limits this effect.
Another way of implementing a high-frequency negative feedback includes using the output signal of the VCO to periodically charge and discharge a capacitor with the frequency of the output signal of the VCO. The mean value of the charging voltage of which, which is a function of the frequency of the output signal of the VCO, and is added to the regulation voltage VR.
Recently, as described in the publication:
IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 30 No. 4, APR 1995, in the article by Jose Alvarez et al. entitled "A wide-bandwidth Low-voltage PLL for Power PC.TM. Microprocessor", pages 383-391, it was proposed, for the purpose of achieving a high noise rejection from the supply voltage, to construct the VCO with a pair of ring oscillators identical to one another and both being voltage-controlled and mutually synchronous by a cross-coupling of the output delay cells of the two rings, in such a manner that the two oscillators operate in phase opposition.
The output signals from the two ring oscillators, which are mutually dephased by 180.degree., are applied on the input side to a differential stage which restores the full excursion of the output signal from the supply voltage Vcc to earth. Even though no explanation is given in the cited document, it is deduced from an analytical study of the circuit that the noise rejection is due to the cross-synchronization of the two rings which, as explained further on, forces the synchronization cells to operate with a propagation and synchronization delay. This delay is approximately constant or which increases as the supply voltage Vcc-VR of the cells increases, that is to say in the sense opposite to that in which the delay of the other cells varies.
Furthermore, during the synchronization time interval, the conflict between signals applied on the input side to the synchronization cells causes an increase in load on the reference voltage generator and a corresponding variation of the mean value of the regulation voltage VR. This accordingly introduces a high-frequency negative feedback with a modest gain which, nevertheless, cannot be increased without causing an unacceptable reduction of the voltage/frequency conversion gain of the oscillator circuit.